1. Field of the Invention
The present invention relates to a semiconductor memory device fabricated on a semiconductor chip, and more particularly to a memory device provided with a serial addressing circuit for serially reading a plurality of bit locations without address information which is externally applied.
2. Description of the Related Arts
Many kinds of memories have been developed and used widely in accordance with purposes and applications. Among those memories, a memory having a large capacity is advantageously used in a system processing large amount of data such as those for images or voices.
The memory of this kind is not required to operate at a very high speed, but to be fabricated at low cost. Therefore, a memory of serially addressing type has been proposed to minimize the number of external pins so as to reduce the cost.
Since such a memory having a large memory capacity has a wide address space which requires a large address bit length. This makes it necessary to use a great number of address terminals if the conventional address access system is adopted. On the other hand, the image or voice data stored in a memory are practically read out not in an arbitrary order but in a predetermined order. The data are stored in a row in the order to be read-out. Thus, the stored data can be read-out in the order by repeatedly addressing the columns in the order. This sequential addressing can be achieved by using a shift register or a counter to generate successive column addresses. Thus, a plurality bits of data stored in bit lines are sequentially read out one by one by incrementing or decrementing contents of the shift register without using a large number of column address terminals for receiving the column address.
Since the memory device of this kind does not need the large number of address terminals, it can be fabricated at a low cost and used easily. However, in the memory of this kind, it is difficult to know which column is being accessed from the outside of the memory. It is sometimes required to detect or predict the timing point when the sequential access through the columns of the selected row (word) is completed, for selecting a subsequent row or another memory in an interleaved manner at a high speed. Under the above circumstance, it has been proposed to provide in the memory a detection circuit for detecting the access to a predetermined one column other than the last column, e.g. a central column. For this detection, a stage in the shift register corresponding to the predetermined column is connected to the detection circuit through a connection wire. A detection output of the detection circuit is, in turn, applied to a memory controller.
In the above system using the detection circuit, the shift stage corresponding to the central column locates at a central portion of the shift register remote from the last stage of the shift register. Since the memory device has the shift register interposed between two planes of memory element matrices to control the column lines, the detection device cannot be disposed near the central stage but is positioned at; an area near the last stage. Therefore, the wiring from the central stage to the detection circuit is inevitably long, causing an accompany of large stray capacitance. The large stray capacitance causes a time delay on a signal to be transmitted, resulted in a delay of detection. This delay in detection limits the high speed operation of the memory device. Moreover, the large stray capacitance weakens the signal to be transmitted to lose the reliability of operation of the detection.